Undefined
By: Guest | Date: Oct 31 2011 00:23 | Format: VHDL | Expires: never | Size: 4.01 KB | Hits: 954
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- use work.math_pkg.all;
- entity serial_port_receiver_fsm is
- generic(
- CLK_DIVISOR : integer
- );
- port(
- clk, res_n, rx : in std_logic;
- data : out std_logic_vector(7 downto 0);
- data_new : out std_logic
- );
- end serial_port_receiver_fsm;
- architecture behav of serial_port_receiver_fsm is
- type rcv_state is (
- IDLE,
- WAIT_START_BIT,
- GOTO_MIDDLE_OF_START_BIT,
- MIDDLE_OF_START_BIT,
- WAIT_DATA_BIT,
- MIDDLE_OF_DATA_BIT,
- WAIT_STOP_BIT,
- MIDDLE_OF_STOP_BIT
- );
- signal state, next_state: rcv_state;
- signal clk_count, next_clk_count: std_logic_vector(log2c(CLK_DIVISOR) downto 0);
- signal bit_count, next_bit_count: std_logic_vector(2 downto 0);
- signal data_int, next_data_int: std_logic_vector(7 downto 0);
- signal data_out, next_data_out: std_logic_vector(7 downto 0);
- signal data_new_out, next_data_new_out: std_logic;
- begin
- synchronisation: process(clk, res_n)
- begin
- if res_n = '0' then
- state <= IDLE;
- clk_count <= (others => '0');
- bit_count <= (others => '0');
- data <= (others => '0');
- data_new <= '0';
- data_int <= (others => '0');
- elsif clk'event and clk = '1' then
- state <= next_state;
- clk_count <= next_clk_count;
- bit_count <= next_bit_count;
- data_out <= next_data_out;
- data <= next_data_out;
- data_new_out <= next_data_new_out;
- data_new <= next_data_new_out;
- data_int <= next_data_int;
- end if;
- end process synchronisation;
- state_transition: process(rx, clk_count, bit_count)
- begin
- next_state <= IDLE;
- case state is
- when IDLE =>
- if rx = '1' then
- next_state <= WAIT_START_BIT;
- end if;
- when WAIT_START_BIT =>
- if rx = '0' then
- next_state <= GOTO_MIDDLE_OF_START_BIT;
- end if;
- when GOTO_MIDDLE_OF_START_BIT =>
- if clk_count = std_logic_vector(to_unsigned((CLK_DIVISOR/2)-2,clk_count'length)) then
- next_state <= MIDDLE_OF_START_BIT;
- end if;
- when MIDDLE_OF_START_BIT =>
- next_state <= WAIT_DATA_BIT;
- when WAIT_DATA_BIT =>
- if clk_count = std_logic_vector(to_unsigned(CLK_DIVISOR - 2,clk_count'length)) then
- next_state <= WAIT_DATA_BIT;
- end if;
- when MIDDLE_OF_DATA_BIT =>
- if bit_count < std_logic_vector(to_unsigned(7,bit_count'length)) then
- next_state <= WAIT_DATA_BIT;
- elsif bit_count = std_logic_vector(to_unsigned(7,bit_count'length)) then
- next_state <= WAIT_STOP_BIT;
- end if;
- when WAIT_STOP_BIT =>
- if clk_count = std_logic_vector(to_unsigned(CLK_DIVISOR - 2,clk_count'length)) then
- next_state <= MIDDLE_OF_STOP_BIT;
- end if;
- when MIDDLE_OF_STOP_BIT =>
- if rx = '0' then
- next_state <= IDLE;
- elsif rx = '1' then
- next_state <= WAIT_START_BIT;
- end if;
- end case;
- end process state_transition;
- output_logic: process(state,clk_count,bit_count,data_int,data_out,data_new_out)
- begin
- next_clk_count <= clk_count;
- next_bit_count <= bit_count;
- next_data_new_out <= '0';
- next_data_out <= data_out;
- next_data_int <= data_int;
- case state is
- when IDLE =>
- when WAIT_START_BIT =>
- next_bit_count <= (others => '0');
- next_clk_count <= (others => '0');
- when GOTO_MIDDLE_OF_START_BIT =>
- next_clk_count <= std_logic_vector(unsigned(clk_count) + 1);
- when MIDDLE_OF_START_BIT =>
- next_clk_count <= (others => '0');
- when WAIT_DATA_BIT =>
- next_clk_count <= std_logic_vector(unsigned(clk_count) + 1);
- when MIDDLE_OF_DATA_BIT =>
- next_clk_count <= (others => '0');
- next_bit_count <= std_logic_vector(unsigned(bit_count) + 1);
- next_data_int <= rx & data_int;
- when WAIT_STOP_BIT =>
- next_clk_count <= std_logic_vector(unsigned(clk_count) + 1);
- when MIDDLE_OF_STOP_BIT =>
- next_data_new_out <= '1';
- next_data_out <= data_int;
- end case;
- end process output_logic;
- end behav;
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