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By: ram vhdl | Date: Mar 20 2008 10:11 | Format: None | Expires: never | Size: 2.17 KB | Hits: 712

  1. -------------------------------------------------------------------------------
  2. -- Title      : Wishbone Ram Behavioral model
  3. -- Project    : FH-Hagenberg/ESD - Semester 2, Advanced Methods of Verification
  4. -------------------------------------------------------------------------------
  5. -- File       : unitRam-Bhv-ea.vhd
  6. -- Author     : Copyright 2008 Wolfgang Silbermayr
  7. -- UsrNames   : silwol - Wolfgang Silbermayr
  8. -------------------------------------------------------------------------------
  9. -- Description:
  10. -------------------------------------------------------------------------------
  11.  
  12. library ieee;
  13. use ieee.std_logic_1164.all;
  14. use ieee.numeric_std.all;
  15. use work.global.all;
  16.  
  17. entity Ram is
  18.   generic (
  19.       gDataWidth : natural := 32;
  20.       gAddrWidth : natural := 8);
  21.   port (
  22.       clk_i : in  std_ulogic;
  23.       rst_i : in  std_ulogic;
  24.       adr_i : in  std_ulogic_vector(gAddrWidth-1 downto 0);
  25.       dat_i : in  std_ulogic_vector(gDataWidth-1 downto 0);
  26.       sel_i : in  std_ulogic_vector(gAddrWidth/8-1 downto 0);
  27.       cyc_i : in  std_ulogic;
  28.       stb_i : in  std_ulogic;
  29.       we_i  : in  std_ulogic;
  30.       dat_o : out std_ulogic_vector(gDataWidth-1 downto 0);
  31.       ack_o : out std_ulogic);
  32. end entity Ram;
  33.  
  34. architecture Bhv of Ram is
  35.  
  36.   type mem_array is array(natural range <>)
  37.     of std_ulogic_vector(gDataWidth-1 downto 0);
  38.  
  39. begin
  40.   variable mem : mem_array(0 to (1 << gAddrWith)-1);
  41.  
  42.   ram_behavior : process(clk_i, rst_i) is
  43.   begin
  44.     if rst_i = cActivated then
  45.       ack_o <= cInActivated;
  46.       dat_o <= (others => '0');
  47.     else
  48.       ack_o <= cInActivated;
  49.       dat_o <= (others => 'X');
  50.  
  51.       if cyc_i = cActivated and stb_i = cActivated then
  52.  
  53.         -- TODO get nubmer of cycles to wait on
  54.         -- TODO wait number of waitstates
  55.  
  56.         ack_o <= cActivated;
  57.  
  58.         if we_i = cInActivated then
  59.           dat_o <= mem(adr_i);
  60.           wait until rising_edge(clk_i);
  61.           dat_o <= (others => 'X');
  62.         else
  63.           wait until rising_edge(clk_i);
  64.           mem(adr_i) <= dat_i;
  65.         end if;
  66.         ack_o <= cInActivated;
  67.  
  68.       end if;
  69.  
  70.     end if;
  71.   end process ram_behavior;
  72.  
  73. end architecture Bhv;